1. Field
The present disclosure pertains to the field of integrated circuits. More particularly, the present disclosure pertains to integrated circuits having multiple clock domains and cross-over logic to allow different portions of such integrated circuits to operate in such different clock domains.
2. Description of Related Art
Some integrated circuits allow internal portions to operate faster than the integrated circuit communicates with other components. Such integrated circuits are often referred to as having different clock domains. As semiconductor fabrication improvements are made and various portions of the integrated circuit are fine tuned, it often becomes possible to operate internal portions of such integrated circuits at higher frequencies. However, changing the frequency at which the integrated circuit communicates with other components is typically more difficult because the other components may need to be altered as well.
Accordingly, providing flexible interfaces to allow different clocking domains to continue operating at different frequencies may be advantageous. Such flexible interfaces may allow many different frequencies to be used for an internal clock domain while still fitting within a single or a limited set of external configurations.
FIG. 1a illustrates one prior art integrated circuit 100. The integrated circuit 100 includes a core 120 that operates at a first frequency (fA) and a bus interface 110 that operates at a second frequency (fB). In this prior art processor, cross-over circuitry is used to implement integral fractional ratios of bus to core frequency (n/m). An integral fractional frequency ratio means that one frequency is n/m times the other frequency, where n and m are integers greater than zero. In this case, the bus frequency is n/m times the core frequency. Details of one prior art cross-over circuit are discussed in U.S. Pat. No. 5,471,587.
FIG. 1b illustrates another prior art integrated circuit 130. The integrated circuit of FIG. 1b includes three frequency domains. The first frequency domain 160 operates at the highest frequency (fA). This highest frequency is twice the frequency of a second frequency domain 150 (fB). Such straightforward 2:1 clock frequency crossings allows even higher performance for portions such as the integer arithmetic and logic unit of a microprocessor. The frequency of the first frequency domain 160, however, is directly tied to the frequency of the second frequency domain 150. Additionally, since high performance is often crucial in such an arrangement and because prior art cross-over circuitry for fractional clock domain interfaces may have significant performance penalties, such secondary clock domain crossings typically do not include complex domain crossing logic.
The system of FIG. 1b also includes a bus interface 140 that operates at a third frequency (fC). The bus interface 140 may operate at one of a few integral fractional frequency ratios (n/m) to the second frequency domain 150. This single integral fractional ratio interface only allows two variable frequency domains. A variable frequency domain has an operating frequency that can be adjusted with respect to other frequency domains or held constant while the other domain operating frequencies change. The operating frequency for a variable frequency domain may be directly selectable or may be selected by changing a ratio which defines the operating frequency with respect to that of another frequency domain. In the system of FIG. 1b, the bus interface 140 is one variable frequency domain, and the combination of the fixed-ratio domains, the first frequency domain 160 and the second frequency domain 150, together forms a second variable frequency domain.
Accordingly, prior art integrated circuits, do not implement multiple flexible clock domain interfaces and/or do not have adequately flexible and high performance frequency domain cross-overs.